Semiconductor housing



FIG. 1 is a right side, top and front perspective view of a semiconductor housing showing my new design;

FIG. 2 is a top plan view thereof on a reduced scale;

FIG. 3 is a bottom plan view thereof on a reduced scale;

FIG. 4 is a left side elevational view thereof on a reduced scale;

FIG. 5 is a right side elevational view thereof on a reduced scale;

FIG. 6 is a front elevational view thereof on a reduced scale;

FIG. 7 is a rear elevational view thereof on a reduced scale;

FIG. 8 is a top plan view of second embodiment of my new design, the second embodiment being identical to the first except for the number of leads on the right hand side;

FIG. 9 is a bottom plan view thereof;

FIG. 10 is a top plan view of a third embodiment of my new design, the third design being identical to the first embodiment except for the shape of the two leads on the left hand side;

FIG. 11 is a bottom plan view thereof;

FIG. 12 is a right side, top and front perspective view of a fourth embodiment of my new design;

FIG. 13 is a top plan view thereof on a reduced scale;

FIG. 14 is a front elevational view thereof on a reduced scale;

FIG. 15 is a left side elevational view thereof on a reduced scale;

FIG. 16 is a right side, top and front perspective view of a fifth embodiment of my new design, the fifth embodiment being identical to the first embodiment except for the flat top surface;

FIG. 17 is a right side, top and front perspective view of a sixth embodiment of my new design;

FIG. 18 is a top plan view thereof on a reduced scale;

FIG. 19 is a bottom plan view thereof on a reduced scale;

FIG. 20 is a left side elevational view thereof on a reduced scale;

FIG. 21 is a right side elevational view thereof on a reduced scale. 

The ornamental design for a semiconductor housing, as shown and described. 